1. Field of the Invention
The present invention relates to a transmitter/receiver capable of infrared-communicating with a personal computer, a portable information terminal and other home use instruments, which has an infrared communication function, and more specifically to a modulation/demodulation method and apparatus for transferring a large amount of data by use of infrared.
2. Description of Related Art
A prior art modulation/demodulation system used in an infrared communication of a personal computer is one called a "4 pulse position modulation" (called a "4PPM " hereinafter). As prescribed in "Infrared Data Association Serial Infrared Physical Layer Link Specification", the 4PPM is that an input signal of two bits is modulated to a modulation signal in which one word consists of four bits. At this time, the modulation signal has a pulse on only one bit within each one word, and the position of the pulse in the word is different from one pattern of an input signal to another.
Referring to FIG. 9, there is shown a diagram illustrating a correspondence between the input signal and the modulation signal in the 4PPM system. In the modulation signal, a first bit is called "a", and a second bit is called "b". A third bit is called "c" and a fourth bit is called "d". When the two bits of the input signal is constituted of "00", the pulse exists on the first bit "a" in the corresponding modulation signal. When the two bits of the input signal is constituted of "01", "10" or "11", the pulse exists on the second bit "b", the third bit "c" or the fourth bit "d" in the corresponding modulation signal.
Referring to FIG. 10, there is shown a first timing chart illustrating the input signal and the modulation signal in the 4PPM system. In FIG. 10, the modulation signal is in synchronism with the rising of a modulation clock, and the modulation signal is constituted of four bits (namely, one word) with four modulation clocks. On the other hand, the input signal is in synchronism with the rising of an input clock, and the input signal is constituted of two bits (namely, one word) with two input clocks. Accordingly, the frequency of the input clock is a half the frequency of the modulation clock. For example, if the input clock is 4 MHz, the modulation clock becomes 8 MHz. In this case, the transfer rate is 4 Mbps (Mega bit per second).
In FIG. 10, similarly to FIG. 9, a first bit, a second bit, a third bit and a fourth bit in one word of the modulation signal are called "a", "b", "c" and "d", respectively. The first word corresponds to the input signal "00" and the modulation signal has the pulse positioned on the first bit "a". The second word corresponds to the input signal "01" and the modulation signal has the pulse positioned on the second bit "b". The third word corresponds to the input signal "10" and the modulation signal has the pulse positioned on the third bit "b". The fourth word corresponds to the input signal "11" and the modulation signal has the pulse positioned on the fourth bit "d".
Referring to FIG. 11, there is shown a second timing chart illustrating the input signal and the modulation signal in the 4PPM system. FIG. 11 illustrates the waveform of the modulation signal in a situation in which the fourth word shown in FIG. 10 follows the first word shown in FIG. 10. In FIG. 11, the modulation signal has the pulse positioned at the bit "a" in the first word and the pulse positioned at the bit "d" in the fourth word. In this case, six bits having no pulse continues from the bit "b" of the first word to the bit "c" of the fourth word. In the 4PPM , the bit width of continuing bits having no pulse is 6 bits as shown in FIG. 11.
Referring to FIG. 12, there is shown a third timing chart illustrating the input signal and the modulation signal in the 4PPM system. FIG. 12 illustrates the waveform of the modulation signal in a situation in which the first word shown in FIG. 10 follows the fourth word shown in FIG. 10. In FIG. 12, the modulation signal has the pulse positioned at the bit "d" in the fourth word and the pulse positioned at the bit "a" in the first word. In this case, only two bits having the pulse continues at maximum. In the 4PPM , the bit width of continuing bits having the pulse is 2 bits as shown in FIG. 11.
In the infrared communication, the pulse width of the modulation signal is influenced with a response characteristics of an infrared light emitting diode. In other words, the pulse width of the modulation signal emitted from the infrared light emitting diode and therefore influenced by the response characteristics of the infrared light emitting diode becomes wide or narrow in comparison with an inherent pulse width of the modulation signal.
If many bits of the pulse continue, or if many bits of no pulse continue, the modulation signal influenced by the response characteristics of the infrared light emitting diode is not synchronized with the modulation clock, with the result that a normal communication cannot be obtained. In the 4PPM , as mentioned above, the continuing bits of the pulse are two bits at maximum, and the continuing bits of no pulse are six bits at maximum. Therefore, they are relatively small. On the other hand, if the frequency of the modulation clock increases, the inherent pulse width of the modulation signal becomes narrow, with the result that the response of the infrared light emitting diode cannot follow the change of the modulation signal, and therefore, a normal communication cannot be obtained. Because of these reasons, the prior art infrared communication adopts the modulation system of the 4PPM , the modulation clock frequency of 8 MHz, and the transfer rate of 4 Mbps .
Incidentally, referring to FIG. 13, there is shown a circuit diagram illustrating one example of a modulation circuit at a transmitter side in the 4PPM system. In FIG. 13, Reference Numeral 250 designates a two-bit serial-to-parallel conversion circuit, and Reference Numeral 251 denotes a decoder. Reference Numeral 252 indicates a four-bit parallel-to-serial conversion circuit. Reference Numeral 10-3 shows an input signal supplied to a data input of the two-bit serial-to-parallel conversion circuit 250, and Reference Numeral 11-3 designates an input clock supplied to a clock input of the two-bit serial-to-parallel conversion circuit 250. Reference Numeral 12-3 denotes a modulation clock supplied to a clock input of the four-bit parallel-to-serial conversion circuit 252, and Reference Numeral 13-3 indicates a modulation signal outputted from a data output of the four-bit parallel-to-serial conversion circuit 252.
The above mentioned decoder 251 comprises inverters 351 and 352 and AND gates 451, 452, 453 and 454, which are connected as shown. An input of the inverter 351 is connected to a first output of the two-bit serial-to-parallel conversion circuit 250, and an input of the inverter 352 is connected to a second output of the two-bit serial-to-parallel conversion circuit 250. The AND gate 451 has inputs connected to the first output and the second output of the two-bit serial-to-parallel conversion circuit 250, respectively. The AND gate 452 has inputs connected to an output of the inverter 351 and the second output of the two-bit serial-to-parallel conversion circuit 250, respectively. The AND gate 453 has inputs connected to the first output of the two-bit serial-to-parallel conversion circuit 250 and an output of the inverter 352, respectively. The AND gate 454 has inputs connected to the output of the inverter 351 and the output of the inverter 352, respectively. The four-bit parallel-to-serial conversion circuit 252 has first, second, third and fourth data inputs connected to an output of the AND gates 451, 452, 453 and 454, respectively.
In the above mentioned construction, when the two-bit serial-to-parallel conversion circuit 250 captures the two-bit serial data "00" as the input signal 10-3 in synchronism with the input clock 11-3, the two-bit serial-to-parallel conversion circuit 250 outputs "0" from the first output and "0" from the second output. In the decoder 251 receiving the outputs of the two-bit serial-to-parallel conversion circuit 250, the AND gate 451 outputs "0", the AND gate 452 outputs "0", the AND gate 453 outputs "0", and the AND gate 454 outputs "1".
The four-bit parallel-to-serial conversion circuit 252 captures the outputs of the AND gates 451, 452, 453 and 454 at their first, second, third and fourth data inputs, respectively, in parallel. In synchronism with the modulation clock 12-3, the four-bit parallel-to-serial conversion circuit 252 serially outputs the fourth data input, the third data input, the second data input and the first data input in the named order as the modulation signal 13-3. Namely, the four-bit serial data "1000" is outputted as the modulation signal 13-3. This operation shows the modulation of the first word shown in FIG. 10.
Similarly, when the two-bit serial-to-parallel conversion circuit 250 captures the two-bit serial data "01" as the input signal 10-3, the AND gate 451 outputs "0", the AND gate 452 outputs "0", the AND gate 453 outputs "1", and the AND gate 454 outputs "0". Namely, the four-bit serial data "0100" is outputted as the modulation signal 13-3. This operation shows the modulation of the second word shown in FIG. 10.
Similarly, when the two-bit serial-to-parallel conversion circuit 250 captures the two-bit serial data "10" as the input signal 10-3, the AND gate 451 outputs "0", the AND gate 452 outputs "1", the AND gate 453 outputs "0", and the AND gate 454 outputs "0". Namely, the four-bit serial data "0010" is outputted as the modulation signal 13-3. This operation shows the modulation of the third word shown in FIG. 10.
Similarly, when the two-bit serial-to-parallel conversion circuit 250 captures the two-bit serial data "11" as the input signal 10-3, the AND gate 451 outputs "1", the AND gate 452 outputs "0", the AND gate 453 outputs "0", and the AND gate 454 outputs "0". Namely, the four-bit serial data "0001" is outputted as the modulation signal 13-3. This operation shows the modulation of the fourth word shown in FIG. 10.
Referring to FIG. 14, there is shown a circuit diagram illustrating one example of a demodulation circuit at a receiver side in the 4PPM system. In FIG. 14, Reference Numeral 253 designates a four-bit serial-to-parallel conversion circuit, and Reference Numeral 254 denotes a encoder. Reference Numeral 255 indicates a two-bit parallel-to-serial conversion circuit. Reference Numeral 13-4 shows a modulation signal supplied to a data input of the four-bit serial-to-parallel conversion circuit 253, and Reference Numeral 124 designates a modulation clock supplied to a clock input of the four-bit serial-to-parallel conversion circuit 253. Reference Numeral 11-4 denotes an input clock supplied to a clock input of the two-bit parallel-to-serial conversion circuit 255, and Reference Numeral 104 indicates an output signal outputted from a data output of the two-bit parallel-to-serial conversion circuit 255.
The encoder 252 includes two OR gates 551 and 552 connected as shown. The OR gate 551 has two inputs connected to a first output and a third output of the four-bit serial-to-parallel conversion circuit 253, respectively. The OR gate 552 has two inputs connected to the first output and a second output of the four-bit serial-to-parallel conversion circuit 253, respectively. An output of the OR gates 551 and 552 are connected to a first data input and a second data input of the two-bit parallel-to-serial conversion circuit 255, respectively.
With the above mentioned arrangement, when the four-bit serial-to-parallel conversion circuit 253 captures the four-bit serial data "1000" as the modulation signal 13-4 in synchronism with the modulation clock 12-4, the four-bit serial-to-parallel conversion circuit 253 outputs "0", "0", "0" and "1" from the first output, the second output, the third output and the fourth output, respectively. In the encoder 254 receiving the outputs of the four-bit serial-to-parallel conversion circuit 253, the OR gate 551 outputs "0" and the OR gate 552 outputs "0". The two-bit
parallel-to-serial conversion circuit 255 receives the output of the OR gate 551 at its first data input and the output of the OR gate 552 at its second data input, and serially outputs the second data input and the first data input in the named order in synchronism with the input clock 11-4. In other words, the two-bit serial data "00" is outputted as the output signal 10-4. This operation shows the demodulation of the first word shown in FIG. 10.
Similarly, when the four-bit serial-to-parallel conversion circuit 253 captures the four-bit serial data "0100" as the modulation signal 13-4, the OR gate 551 outputs "1" and the OR gate 552 outputs "0". Namely, the two-bit serial data "01" is outputted as the output signal 10-4. This operation shows the demodulation of the second word shown in FIG. 10.
Similarly, when the four-bit serial-to-parallel conversion circuit 253 captures the four-bit serial data "0010" as the modulation signal 13-4, the OR gate 551 outputs "0" and the OR gate 552 outputs "1". Namely, the two-bit serial data "10" is outputted as the output signal 10-4. This operation shows the demodulation of the third word shown in FIG. 10.
Similarly, when the four-bit serial-to-parallel conversion circuit 253 captures the four-bit serial data "0001" as the modulation signal 134, the OR gate 551 outputs "1" and the OR gate 552 outputs "1". Namely, the two-bit serial data "11" is outputted as the output signal 10-4. This operation shows the demodulation of the fourth word shown in FIG. 10.
In the 4PPM system, the data transfer rate is determined by the frequency of the input clock. The prior art 4PPM system has the input clock frequency of 4 MHz, the modulation clock frequency of 8 MHz and the data transfer rate of 4 Mbps . In this case, the frequency of the input clock is a half the frequency of the modulation clock. In the prior art 4PPM system, therefore, since data is transmitted after the two-bit input signal is modulated to the four-bit modulation signal, the data transfer rate is low.
Furthermore, when the infrared communication is performed in the 4PPM system, if it is attempted to increase the frequency of the modulation clock in order to elevate the data transfer rate, the response characteristics of the infrared light emitting diode becomes unable to follow the change of the modulation signal. Therefore, it is impossible to increase the frequency of the modulation clock.